1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having recess channels and asymmetrical junctions.
2. Description of the Related Art
As the integration of semiconductor devices increase, deterioration in the characteristics of semiconductor devices due to short channel effects is of primary concern. Further, in a process for forming a shallow trench isolation (STI) film, an inverse narrow width effect (INWE) due to the edges of an active region is increased. Accordingly, leakage current characteristics are generated in transistors, thereby causing the deterioration in the characteristics of the semiconductor device, for example, deterioration in the refresh or data retention time of a dynamic random access memory (DRAM). Thus, a semiconductor device having recess channels with an increased length without increasing the density of the dopant on a semiconductor substrate has been proposed. In a method for manufacturing the semiconductor device having the recess channels, channel regions of the semiconductor substrate are recessed to a designated depth and a stack is formed on the recessed channel regions, thereby increasing the length of the channels in a vertical direction. That is, since the effective channel length is increased in proportion to the recessed length of the channel regions of the semiconductor substrate, it is possible to assure the margin of a short channel without increasing the density of the dopant in the channel regions, thereby preventing the deterioration in the refresh characteristics of the DRAM.
In a semiconductor device, particularly a DRAM, storage nodes junction and a bit line junction are electrically connected to storage nodes of a capacitor and the bit line respectively. Leakage current in the storage nodes junction connected to the storage nodes of the capacitor deteriorates the refresh characteristics of the DRAM. Recently, p-type impurity ions for adjusting the threshold voltage, for example, B ions or BF2 ions are implanted into the semiconductor substrate under the condition that the storage nodes junction are cut off, thereby increasing the width of the depletion region in storage node or source junction only, thus decreasing an electric field in the storage noce or source junction only and decreasing the amount of leakage current. Accordingly, a semiconductor device employing the above asymmetrical junctions has been proposed.
FIGS. 1A and 1B are sectional views illustrating one conventional method for manufacturing a semiconductor device having asymmetrical junctions.
First, with reference to FIG. 1A, a mask film pattern 12 for adjusting the threshold voltage and forming asymmetrical junctions is formed on a semiconductor substrate 10, an active region of which is restricted by shallow trench isolation (STI) films 11. The mask film pattern 12 includes an opening 12′ for exposing portions of the semiconductor substrate 10 other than portions of an active region of the semiconductor substrate 10 connected to the storage nodes. Then, as shown by the arrow in FIG. 1A, an impurity region 13 for adjusting the threshold voltage is formed by an ion implantation process using the mask film pattern 12 as an ion implantation mask.
Thereafter, as shown in FIG. 1B, after the mask film pattern (12 in FIG. 1A) is eliminated, a gate stack 14 is formed on the semiconductor substrate 10 using conventional methods. The gate stack 14 is a stacked sequentially structured including a gate insulating film pattern 14a, a gate conductive film pattern 14b, a metal silicide film pattern 14c, and an insulating capping layer pattern 14d. Then, although not shown in the drawings, an ion implantation process and an impurity diffusion process for forming source and bit line junctions are performed. When the source and bit line junctions are formed through the ion implantation process and the impurity diffusion process, an impurity region 13 for adjusting the threshold voltage is partially formed on the semiconductor substrate 10, thereby forming the source and bit line junctions having asymmetrical junctions.
In the above conventional method, the position of the impurity region 13 for adjusting the threshold voltage is changed by the misalignment of the mask film pattern (12 in FIG. 1A). The change in position of the impurity region 13 is undesirable, and causes the threshold voltages of transistors not to be uniformly maintained. That is, a left-biased impurity region 13a generated by misalignment of the mask film pattern (12 in FIG. 1A) causes the threshold voltage of a right transistor (B) to be lower than the threshold voltage of a left transistor (A). On the other hand, a right-biased impurity region 13b generated by the misalignment of the mask film pattern (12 in FIG. 1A) causes the threshold voltage of the left transistor (A) to be lower than the threshold voltage of the right transistor (B).
FIG. 2 is a sectional view illustrating another conventional method for manufacturing a semiconductor device having asymmetrical junctions.
The conventional method as shown in FIG. 2 is the same as that as shown in FIGS. 1A and 1B. However, in the conventional method of FIG. 2, impurity ions for adjusting threshold voltage are implanted onto the overall surface of the semiconductor substrate 10 without using a separate mask film pattern. Then, after the gate stack 14 is formed on the semiconductor substrate 10, a mask film pattern 15 for exposing a portion of the semiconductor substrate 10 exposed by the gate stack 14 is formed. Here, the exposed portion of the semiconductor substrate 10 is not connected to a storage node, but is connected to a bit line. An additional ion implantation process is performed using the mask film pattern 15 as an ion implantation mask film. Then, after the mask film pattern 15 is eliminated, an impurity ion implantation and diffusion process forming source and bit line junctions is performed.
In this case, as the integration of semiconductor devices is increased, an interval between the semiconductor devices is narrowed, thereby causing difficulty of definately defining a mask film pattern for ion implantation due to the scum on a mask film such as a photosensitive film.